1. Field of the Invention
This invention relates to the field of computer systems and, more particularly, to distributed simulation environments.
2. Description of the Related Art
Generally, the development of components for an electronic system such as a computer system includes design verification of the components, which may be accomplished, for example, by simulation of models of the components. During simulation, the specified functions of each component may be tested and, when incorrect operation (a bug) is detected, the model of the component may be changed to generate correct operation. Once design verification is complete, the model may be fabricated to produce the corresponding component. Since many of the bugs may have been detected in design verification, the component may be more likely to operate as specified and the number of revisions to hardware may be reduced. Simulation models are frequently described in a hardware description language (HDL) such as Verilog, VHDL, etc.
Originally, simulations of electronic systems were performed on a single computing system. However, as the electronic systems (and the components forming systems) have grown larger and more complex, single-system simulation has become less desirable. The speed of the simulation (in cycles of the electronic system per second) may be reduced due to the larger number of gates in the model which require evaluation. Additionally, the speed may be reduced as the size of the electronic system model and the computer code to perform the simulation may exceed the memory capacity of the single system. In some cases, the simulators may not be capable of simulating the entire model. As the speed of the simulation decreases, simulation throughput is reduced.
To address these issues, distributed simulation has become more common. Generally, a distributed simulation system includes two or more computer systems (i.e. nodes) simulating portions of an electronic system in parallel. Furthermore, each node must communicate with other nodes to transfer information between different simulated portions of the electronic system. More particularly, a distributed simulation system may sample output signals from the portions of the system simulated by each node and communicate the corresponding signal values to other nodes. The received signal values are then driven as inputs to the models in those other nodes.
When a complex electronic system is partitioned into portions for design verification using simulations, in many cases the amount of processing required to simulate a given portion may differ from the amount of processing required to simulate another portion. As coordination and/or synchronization between different nodes involved in the distributed simulation may be required after each node has completed processing for a particular simulated time interval, a given node may be unable to continue simulation until all other nodes have also completed processing for the same interval. Thus, the overall simulation throughput of a distributed simulation system may be limited by the speed of the slowest node in the system. Accordingly, nodes capable of quickly verifying the design of relatively large portions of a simulated electronic system in a cost-effective manner, while at the same time coordinating and synchronizing with other distributed simulation nodes and allowing for flexible reconfiguration, may be desirable.